A power semiconductor device requires a high withstand voltage and a high figure of merit (FOM: Figure Of Merit). The figure of merit is under the control of a conduction loss due to an on-resistance and a switching loss in a turn-on state, and is expressed by an inverse number of a product of an on-resistance Ron and an input capacitance Ciss (Source Short-circuit Input Capacitance). In general, the on-resistance Ron and the input capacitance Ciss are traded off.
As a conventional power semiconductor device, an insulating gate field effect transistor of which the electric field concentration is moderated by a vertical field plate structure to achieve a high withstand voltage is known.
In the semiconductor device, a trench is formed in an N-type semiconductor layer on a drain layer. A field plate electrode is buried into the trench through a thick field plate insulating film. The field plate electrode is electrically connected to a source layer.
A gate electrode is buried into an upper portion of the trench through a gate insulating film to sandwich the field plate electrode through an insulating film. A P-type base layer is formed on an upper portion of an N-type semiconductor layer adjacent to the trench, and an N-type source layer is formed on the upper portion of the base layer.
As a result, it is a problem in that an input capacitance Ciss increases due to an increase of an inter-electrode capacitance between the gate electrode and the field plate electrode increases. For this reason, it is a problem that it is impossible to obtain a high figure of merit due to an increase of a product of the on-resistance Ron and the input capacitance Ciss.